Tradeoffs and optimization in analog CMOS design
Material type: TextPublication details: Chichester John Wiley &Sons 2008DDC classification:- 621.38152 BIN
Item type | Current library | Collection | Call number | Status | Date due | Barcode | Item holds |
---|---|---|---|---|---|---|---|
Reference Books | LRC, IIT Indore 3rd Floor - Reference Collection | Reference | 621.38152 BIN (Browse shelf(Opens below)) | Not For Loan | 8517 |
Total holds: 0