CMOS : Circuit design, layout, and simulation (Record no. 3890)
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| 000 -LEADER | |
|---|---|
| fixed length control field | 00441nam a2200157Ia 4500 |
| 005 - DATE AND TIME OF LATEST TRANSACTION | |
| control field | 20190429162335.0 |
| 008 - FIXED-LENGTH DATA ELEMENTS--GENERAL INFORMATION | |
| fixed length control field | 170106s2010||||xx |||||||||||||| ||und|| |
| 020 ## - INTERNATIONAL STANDARD BOOK NUMBER | |
| International Standard Book Number | 9788126520374 |
| 082 ## - DEWEY DECIMAL CLASSIFICATION NUMBER | |
| Classification number | 621.392 |
| Item number | BAK |
| 100 ## - MAIN ENTRY--PERSONAL NAME | |
| Personal name | Baker, Jacob R |
| 245 #0 - TITLE STATEMENT | |
| Title | CMOS : Circuit design, layout, and simulation |
| 260 ## - PUBLICATION, DISTRIBUTION, ETC. | |
| Place of publication, distribution, etc. | New Delhi |
| Name of publisher, distributor, etc. | Wiley & IEEE Press |
| Date of publication, distribution, etc. | 2010 |
| 300 ## - PHYSICAL DESCRIPTION | |
| Extent | xxxiii, 1038 p.; 23 cm |
| 650 ## - SUBJECT ADDED ENTRY--TOPICAL TERM | |
| Topical term or geographic name entry element | Electrical Engineering |
| 942 ## - ADDED ENTRY ELEMENTS (KOHA) | |
| Koha item type | Book |
| Source of classification or shelving scheme | Dewey Decimal Classification |
| Withdrawn status | Lost status | Source of classification or shelving scheme | Damaged status | Not for loan | Home library | Current library | Shelving location | Date acquired | Source of acquisition | Total Checkouts | Total Renewals | Full call number | Barcode | Date last seen | Date last checked out | Price effective from | Koha item type |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dewey Decimal Classification | LRC, IIT Indore | LRC, IIT Indore | 2nd Floor - General Stack | 06/01/2017 | PO No. 1 ; Vendor: VSP Books Int., New Delhi ; Bill No. VS1492, dt.25.11.2010; Price: INR 479 | 14 | 4 | 621.392 BAK | 3890 | 11/05/2022 | 12/04/2022 | 06/01/2017 | Book |
